BYPASS_CLK_SRC=REF_CLK_24M
Analog USB2 480MHz PLL Control Register
| DIV_SELECT | This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22. |
| EN_USB_CLKS | 0: 8-phase PLL outputs for USBPHY1 are powered down |
| POWER | Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. |
| ENABLE | Enable the PLL clock output. |
| BYPASS_CLK_SRC | Determines the bypass source. 0 (REF_CLK_24M): Select the 24MHz oscillator as source. 1 (CLK1): Select the CLK1_N / CLK1_P as source. |
| BYPASS | Bypass the PLL. |
| LOCK | 1 - PLL is currently locked. 0 - PLL is not currently locked. |